Method of controlling a stepping motor

ABSTRACT

A method and a device for controlling a stepping motor in which the width of step and the direction of rotation of the stepping motor are determined in a controller and sent to a control arrangement for controlling the stepping motor. Upon each step clock signal from the controller, a step is carried out. The step width output by the controller is divided by the control circuit into a plurality of smaller partial steps the step width of which is smaller than the step width output by the controller, and these partial steps are sent in several time-staggered pulses by the control circuit to the stepping motor.

BACKGROUND INFORMATION

From the article "The Stepping Motor and the Duration of Its Step,"Feinwerktechnik und Messtechnik 99(7-8):327-332, 1991, by Klaus Mayer, astepping motor is known which has a permanent-magnet rotor arranged on amotor shaft, the rotor rotating within the rotating magnetic field oftwo coil systems. For the control of this motor, the coils are acted onalternately by current. For each sampling of action of the current, therotor places itself in a given stable position. Movement from one suchstable position into the following stable position in the direction ofrotation of the rotor for another sampling of action of the current isreferred to as a step. In this connection, one distinguishes betweendifferent types of stepping operation. There are known in thisconnection full-step operation, half-step operation, and micro-stepoperation. Micro-step operation is characterized by the fact that thecurrent samplings for the coils of the stepping motor extend indiscretely approximated sinusoidal curves. The division of the rotationof the rotor into individual micro-steps together with a maximum speedof revolution with which the rotor is to rotate gives the maximumcontrol-step clock frequency with which the stepping motor is to becontrolled. For example, a micro-step of 1/32°, referred to the pointershaft of a geared stepping motor, with a maximum angular speed ofrotation of the pointer of 400°/sec results in a control-step clockfrequency of 12.8 kHz for the stepping motor.

SUMMARY OF THE INVENTION

The method of the present invention for controlling a stepping motor hasthe advantage, as compared to the related art, that, despite a lowcontrol-step clock frequency, a higher control resolution in the form ofsmaller partial steps is obtained, as a result of which the noisedeveloped by the stepping motor is less, particularly at low speeds ofrotation. Furthermore, the movement of a pointer which is driven inrotation by the stepping motor is more uniform. Furthermore, the expensefor the circuitry is less, since circuits which provide a lowercontrol-step clock frequency are generally less expensive and morereliable. A control circuit which is adapted to be connected in front ofthe stepping motor and is as a rule a microcontroller is thus relievedby the method from tasks which require lengthy calculating times.

If the first partial step is carried out with the step timing, theconstruction of the circuit is thereby simplified, since the step timingitself can serve for the triggering of the first partial step.

If the partial steps are carried out with a constant time delay aftereach first partial step, a particularly low circuit expense results forthe production of the partial-step timing pulses.

If the time delay between the partial steps is decreased with increasingstep clock frequency, there is thus obtained a constant number ofpartial steps for each full step, as a result of which there is noreduction in the resolution into partial steps upon an increase in thestep timing frequencies.

The use of a phase-locked loop (PLL) circuit for the production of thepartial-step clock frequency is particularly advantageous, since, on theone hand, there is thereby obtained the automatic following up of thepartial-step clock frequency with the full step frequency and, on theother hand, divider-unrelated frequency ratios between partial-stepclock frequency and step clock frequency can also be obtained.

The device of the present invention for controlling a stepping motor hasthe advantage, over the related art, that the control device need haveonly a low control step clock frequency and that, in this connection,nevertheless a higher control resolution in the form or smaller partialsteps takes place, as a result of which the noise developed by thestepping motor is less, particularly at low speeds of rotation.

A monostable flip-flop constitutes a particularly economical means ofobtaining a constant period of delay between the partial-step pulses.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a circuit for the control of astepping motor according to the present invention.

FIG. 2 illustrates an example of the sequence of several control-steptiming pulses and of the partial steps then taking place.

FIG. 3 illustrates another embodiment of a circuit for the control of astopping motor according to the present invention.

DETAILED DESCRIPTION

FIG. 1 shows a first embodiment of the present invention in which thebasic concept of the invention is integrated in a control circuit 20.This control circuit 20 is arranged between a controller 13 and astepping motor 9 and effects the control of the stepping motor, with theadvantages explained in the introduction to the specification. Thecontroller 13 has an input Xi which is connected with a desired-angleoutput Xo or a desired-position transducer 11, the signals of a sensor12 being fed to a sensor input Si of the desired-position transducer 11.Two outputs of controller 13 are fed to control circuit 20. They are thedirection output Do, which indicates the direction of rotation, and theclock output To, which is responsible for the step advance. Directionoutput Do of controller 13 is connected to a direction input Dir of acounter 1, and clock output To of controller 13 is connected to a clockinput T of counter 1. The step-advance signal of clock output To isfurthermore connected to reset input C1 of a monostable flip-flop 2.Monostable flip-flop 2 has a positive output Q and an inverted outputQ'. The positive output Q is connected via a first output line 3 to afirst input B of a controlled changeover switch 5. Similarly, invertedoutput Q' is connected via a second output line 4 to a second input A ofthe controlled changeover switch (multiplexer) 5. Furthermore, aconnection is provided between direction output Do and a selector inputS of the controlled changeover switch 5 which counts the bits 1 to ncorresponding to the angular position for both directions of rotation.The controlled changeover switch 5 has a selection output Z which isconnected to a counter 21. Here, the value supplied by selection outputZ is assigned a bit position, namely the lowest value bit 0 in a binarycoded value. The content of counter 21 is then continued with thecontent of counter 1. Since counter 1 supplies the bit positions bit nto 1, the one composite binary number with the bit positions bit 0 to nresults at an interconnection point. This common counter reading is fedto a counter input C of an allocating means 6! allocating device 6 andfurthermore, via an actual-position transducer 14, to a position input Pof controller 13. Allocating means 6! Allocating device 6 has a firstoutput A1 and a second output A2, which outputs are connected topulse-width modulators 7, 17 respectively. Pulse-width modulators 7, 17are connected to corresponding coils 8, 18 respectively, which serves toprovide the rotating magnetic field for a stepping motor 9.

Sensor 12 serves to detect a measurement value which is to be displayed,for example the speed of revolution of a motor vehicle engine. Theresult of the measurement by the sensor 12 passes, via the sensor inputSi, to the desired-position transducer 11 in which an allocating of thedesired angle α_(s) to the measured value takes place. Such anallocating can be effected, for instance, by means of a stored table.The desired angle α_(s) corresponds to the position which is to be movedto by the stepping motor 9 so that the measurement value measured can bemade known to an observer by a pointer on a dial, the pointer beingmounted on a stepping motor 9 by which it is driven in rotation. Incontroller 13, the difference angle Δα is calculated by formation of thedifference between the desired angle α_(s) and the actual angle α_(I),and thereupon the number of steps necessary to pass over this angle iscalculated. Controller 13 furthermore contains a clock generator which,in accordance with the calculated number of steps, provides this samenumber of clock pulses for the step timing for control of stepping motor9. In this connection, it may in particular be provided that the stepclock frequency also increases with an increase in the difference angleΔα. In this way, a behavior of the pointer is produced which is pleasingto the eye of the observer, since the measure of moving over a largeangle with a high speed of revolution and over a small angle with asmall speed of revolution results in a turning behavior of the pointerwhich has been found pleasing by the viewer. From the sign of thedifference angle Δα, the controller 13 furthermore determines thedirection of rotation in which the rotor of the stepping motor 9 is tomove. The direction of rotation is made known in the form a binarydirection signal via direction output Do on the one hand to counter 1and, on the other hand, to controlled changeover switch 5. The stepclock signal which serves via the clock input T of the counter 1 for theadvancing of counter 1 serves furthermore for the control of monostableflip-flop 2. If the latter is at rest, then a logical high signal(logical 1) is present at the positive output Q and a logical low signal(logical 0) is present at the inverted output Q'. If a positivetime-pulse flank occurs on reset input CL, then monostable flip-flop 2is reset for a predetermined length of time, i.e. output Q is set tological 0 and inverted output Q' is set to logical 1. For positivedirection of counting, the direction signal produces at the selectioninput S of controlled changeover switch 5 a switching of input B toselection output Z. In this way, a connection is present betweenpositive output Q and counter input C. As soon as the predeterminedlength of time which has been set in the monostable flip-flow 2 hasexpired, positive output Q flips back to the logical high level.Selection output Z of controlled changeover switch 5 is brought to acounter 21 which is combined as lowest value bit 0 with the counterreading bit n--bit 1 of the counter 1--to form a single counter readingat interconnection point 22. Selection output Z thus forms, via counter21, the lower-value part of the common counter reading atinterconnection point 22 and the counter reading of counter 1 forms thehigher-value part of the common counter reading at interconnection point22 so that the counter reading with the positions bit n-bit 0 is presentat the interconnecting point 22 and arrives, on the one hand, at counterinput C of allocating means 6! allocating device 6 and, on the otherhand, at position input P of controller 13. In allocating means 6!allocating device 6, the common counter reading is associated withcontrol voltage values which are fed via allocating means! allocatingdevice outputs A1, A2, to pulse-width modulators 7, 17. The allocationin allocating means 6! allocating device 6 may take place, for instance,again via a table which is stored there. However, conversion by means ofan algorithm running in allocating means 6! allocating device 6 is alsopossible. In the pulse-width modulators 7, 17 the arriving amplitudevalues are converted into pulse-width modulated signals which are fed tocoils 8, 18. In this way, coils 8, 18 receive precisely the currentwhich is necessary in order to arrive at the next position valuecorresponding to the common counter reading. Furthermore, the commoncounter reading arrives as actual-position value at controller 13 viaposition input P.

With this circuit the result is obtained that, upon the further advanceof the rotor with each pulse of the step clock signal the step iscarried out in the form of two partial steps. The first of these twopartial steps is carried out here in synchronism with the step timing,while the second partial step is carried out as a function of theduration of the flip of monostable flip-flop 2. In this connectioncounter 1 is responsible for the counting the full steps, whilecontrolled changeover switch 5 contains the lowest value bit of thecounting process and switches it accordingly. The output signal ofcontrolled changeover switch 5 and that of counter 1 together form thecommon counter reading for partial steps which arrives at allocatingmeans 6! allocating device 6, so that initially only half a step takesplace and, after expiration of the duration of the flip, the second halfstep takes place. It is also contemplated to divide the step into morethan two partial steps. Depending on the case of use, full steps, halfsteps or, in particular, also micro-steps can be considered as stepswithin the meaning of the present invention.

As shown by way of example in FIG. 2, a first clock pulse 1° of the stepclock signal (To) results in a first partial step 1' which is followed,spaced in time, by a second partial step 2'. Similarly, a second clockpulse 2° of the step clock signal causes a partial step 3' which in itsturn is followed at a predetermined time interval by another partialstep 4'. This applies in similar manner to the next clock signal 3° withthe partial steps 5' and 6'. If the step clock frequency of the stepclock signal now increases, then the time between two successive clockpulses drops below the value of the flip time of the monostableflip-flop 2. Thus, no further partial step takes place here any longer,but a full step is immediately taken upon the occurrence of the nextclock pulse. Thus, in fact, switching to a coarser step division iseffected. This is generally, however, not critical, since such highangular speeds of revolution normally occur for only a very short time,for instance during the gear change operations of the motor vehicle inthe case of a tachometer. Furthermore, the emission of noise becomes inany event more and more independent of the resolution of the division ofthe step with increasing angular velocity of the rotor.

If one nevertheless would like to avoid losing the division of the stepinto partial steps upon higher angular speeds of revolution, this can bedone by replacing the monostable flip-flop 2 and the controlledchangeover switch 5 by a PLL circuit unit 15.

Such an arrangement is shown in FIG. 3. This arrangement differs fromthe arrangement in FIG. 1 by the following features. Monostableflip-flop 2 is replaced by PLL circuit unit 15. Furthermore, controlledchangeover switch 5 has been replaced by a partial-step counter 10. PLLcircuit unit 15 has a single clock output which is fed to a partialclock input TT of partial-step counter 10. Direction output D is herefurthermore connected to a partial direction input TD of thepartial-step counter 10. Partial-Step counter 10 has a partial-stepcounter output B0 which is fed, together with counter output Bn ofcounter 1, to counter input C of allocating means 6! allocating device6. Partial-step counter output B0 and counter output Bn are in thisconnection combined together to form a single counter reading, thecounter reading of the partial step counter 10 being used as the lowerpart of the common counter reading and the counter reading of thecounter 1 being used as the higher-value part of the common counterreading. This common counter reading is sent to counter input C ofallocating means 6! allocating device 6.

With PLL circuit unit 15, it is possible to reduce the step clockfrequency in the manner that suitable division ratios are used in thedividers which are contained in PLL circuit unit 15. In this way, thepartial-step clock frequency then increases parallel to the step clockfrequency. With embodiments containing PLL circuits, a filtering of thepartial-step clock frequency can furthermore be obtained by suitabledesign, as a result of which an adjusting of the pointer behavior ispossible. Furthermore, PLL circuits are particularly suitable forestablishing divider-independent ratios between the step clock frequencyof the step time signal To and the partial-step clock frequency. Thus itis possible, for instance, to establish a step clock frequency of 12steps per second and a partial-step clock frequency of 32 steps persecond. In this way, practically any desired adaptation betweencontrollers 13 and stepping motors 9 can be obtained. Instead of PLLcircuit unit 15, some other frequency multiplier can also be used, forinstance in digital form.

It is furthermore contemplated that certain functions be taken fromcontroller 13 into the remaining circuit, so that, for instance, onlythe desired angle α_(s) and/or the desired angular speed is fed to thiscircuit and it produces the step time pulses itself. In this way, then,with the circuit described here, the result can be obtained that theresolution for the division of the step for stepping motor 9 be selectedhigh despite only a slight data word width which is used for thedescription of the desired angle α_(s) or the desired angular speed atthe input of the circuit. Pulse width modulators 7, 17 can preferably bedeveloped in the form of push-pull output stages interconnected in theform of an H-bridge. For example this method can be used for gearedstepping motors in display instruments for motor vehicles.

What is claimed is:
 1. A method for controlling a stepping motor fordriving a pointer for an indicating instrument, the method comprisingthe steps of:determining, in a controller, a step width and a directionof rotation of the stepping motor; transmitting the step width and thedirection of rotation from the controller to a control circuit, thecontrol circuit controlling the stepping motor and rotating the steppingmotor one step upon receiving each of a plurality of step clock signalsfrom the controller; dividing, in the control circuit, the step widthreceived from the controller into a plurality of partial steps, whereina further step width of the partial steps is less than the step widthreceived from the controller; generating a composite binary number, thecomposite binary number representing an actual position of each step,wherein the composite binary number includes a lower value bit suppliedby a changeover switch and at least one higher value bit supplied by acounter; transmitting the composite binary number to the controller andto an allocating device, the allocating device transmitting a firstsignal for controlling the stepping motor; converting the compositebinary number to a plurality of time-staggered pulses corresponding tothe plurality of partial steps; and transmitting the time-staggeredpulses from the control circuit to the stepping motor.
 2. The methodaccording to claim 1, wherein a first of the plurality of partial stepsis carried out with a step timing.
 3. The method according to claim 2,wherein a second and third of the plurality of partial steps are carriedout, in each case, with an approximately constant delay time after thefirst partial step.
 4. The method according to claim 3, wherein thedelay time decreases with an increasing step clock frequency.
 5. Themethod according to claim 4, wherein a partial stop clock frequency isderived from the step clock frequency via a PLL circuit unit.